Printed circuit assemblies (PCA's) are typically tested after manufacture to verify the continuity of traces between pads and vias on the board and to verify that components loaded on the PCA perform within specifications. Such printed circuit assembly testing is generally performed with automated in-circuit testers or ICT's and requires complex tester resources. The tester hardware must generally be capable of probing conductive pads, vias and traces on the board under test.
In-circuit testers (ICT) have traditionally used “bed-of-nails” (BON) access to gain electrical connectivity to circuit wiring (traces, nets, pads) for control and observation capability needed for testing. This necessitates having access points within the layout of circuit nets that can be targets for ICT probes. Test access points are usually circular targets with 28 to 35 mil diameter that are connected to traces on the printed circuit board. In some cases these targets are deliberately added test pads, and in other cases the targets are “via” pads surrounding vias already provided in the printed circuit.
Lower diameter targets are increasingly difficult to hit reliably and repeatably, especially when a test fixture may contain several thousand such probes. It is always desirable to use larger diameter targets, but this is in fundamental conflict with the industry trend towards higher densities and smaller geometry devices.
Yet another industry trend is to use higher and higher speed logic families. One Megahertz (MHz) designs became ten MHz designs, then 100 MHz designs, and are now reaching the Gigahertz domain. The increases in logic speed necessitates industry attention to board layout rules for higher-speed interconnects. The goal of these rules is to create a controlled impedance pathway that minimizes noise, crosstalk and signal reflections.
The preferred way of transmitting high-speed data is through differential transmission signals. FIG. 1 illustrates the important layout parameters for a classic pair of differential transmission signal traces 102a, 102b on a portion of a printed circuit board 100. As illustrated, the printed circuit board 100 is formed as a plurality of layers. In the illustrative embodiment, the printed circuit board 100 includes a ground plane 104 layered over a substrate 105, a dielectric 103 layered over the ground plane 104, traces 102a, 102b layered over the dielectric 103, and a solder mask 106 layered over the traces 102a, 102b and exposed surfaces of the dielectric 103. In such a layout, there are a number of critical parameters that affect the impedance of the signal path. These parameters include trace width 110, trace separation 111, trace thickness 112, and dielectric constants of the solder mask and board material. These parameters influence the inductance, capacitance, and resistance (skin effect and DC) of the traces which combine to determine the transmission impedance. It is desired to control this value across the entire run of each trace 102a, 102b. 
In higher speed designs it is also important to control the symmetry of the traces. Ideally, both paths 102a, 102b would be identical in length, as shown in FIG. 2A. However, routing signals on a crowded printed circuit board necessitates curves and bends in the path, which makes matching lengths and symmetries more difficult. In some cases, series components (such as series terminations or DC blocking capacitors) must be included in the path, and these have dimensions that differ from the layout parameters. FIG. 2B, for example, illustrates DC blocking capacitors 114a, 114b on the differential signal traces 102a, 102b. Signals may have to traverse connectors, which add to the difficulties.
Additional difficulties arise when testing is considered. Testing requires tester access to circuit traces at particular probe targets. Layout rules typically require test targets to be at least 50 mils apart and may require the diameter of the test point targets to greatly exceed the width of the traces. FIG. 2C illustrates test targets 115a, 115b symmetrically positioned 50 mils apart on the differential signal traces 102a, 102b. FIG. 2D illustrates test targets 115a, 115b arranged asymmetrically, but at least 50 mils apart, on the differential signal traces 102a, 102b. FIG. 2E illustrates test targets 115a, 115b arranged asymmetrically from the DC blocking capacitors 114a, 114b but at least 50 mils apart on the differential signal traces 102a, 102b, and FIG. 2F illustrates the test targets 115a, 115b implemented on the capacitors 114a, 114b themselves, requiring asymmetrical positioning of the capacitors on the differential signal traces 102a, 102b. 
The positioning of test targets 102a, 102b can be problematic. In many cases the need to keep a minimum separation between targets (typically 50 mils, minimum) is in direct conflict with controlled impedance layout rules. These conflicts lead to either a compromise in controlled impedance integrity, or a forced reduction in target placement with a resulting reduction in testability. As signal speeds continue to rise and board densities increase, this problem will only get worse.